1. Field of the Invention
The present invention is relates generally to matrix array camera apparatus, and to be more specific to an image processing system with matrix array camera apparatus.
2. Description of the Prior Art
At an image processing systems under the prior art, as shown in FIG. 1, a matrix array camera apparatus A is provided which includes a matrix array 1 consisting of 100.times.100 pieces of picture elements P1, 1; P1, 2; . . . ; P1, 100; P2, 1; P2, 2; . . . ; P100, 100 and an image signal processing apparatus B. In the camera apparatus A a shift register 2 is provided which is connected to a vertical clock generator 3 and the matrix array 1, wherein in accordance with the signals from the vertical clock generator 3, the shift register 2 selects the first, second, . . . of the horizontal lined picture element groups of the matrix array 1 in sequence. Further, in FIG. 1, 5 is an odd number transfer member and 6 is an even number transfer member, which are respectively connected with the matrix array 1 and also with a horizontal clock generator 4 as well as a buffer 7. These odd and even number transfer members 5 and 6 receive the contents of picture elements of appropriate address in the horizontal lines (odd and even numbers) as selected on the matrix array 1 by the shift register 2, and send the same to buffer 7 in sequence, in accordance with the horizontal clock signals from the horizontal clock generator 4. Buffer 7 is connected to the odd number transfer member 5, even number transfer member 6, and the horizontal clock generator 4, and in accordance with the horizontal clock signal from the horizontal clock generator 4, it alternatingly outputs the contents of even and odd number transfer numbers 5 and 6 as video or image signal v. While the horizontal clock generator 4 is connected with the odd number transfer member 5 and even number transfer member 6, it also outputs a horizontal address signal aH. Simultaneously with sending the vertical clock signal to shift register 2, the vertical clock generator 3 outputs a vertical address signal aV.
On the other hand, in the image signal processing apparatus B a control circuit B1 is provided which receives the address signals aH and aV as well as the image signal v from the matrix array camera apparatus A i.e. generators 4, 3 and buffer 7. Then, the control circuit B1 sends the image signal v to a temporary memory B2 which contains the same number of memory cells to the picture element number of the matrix array 1 after digital conversion, and the image signal v is stored therein. Readout member B3 receives the output from the memory B2 and digitally calculates the relation between each picture element of the matrix array in the memory B2 and sends the same to a register B4 to be stored therein.
It is noted, however, under the above prior art method it is necessary that the temporary memory B2 requires the same number of memory cells as the picture elements of the matrix array 1. In such respect, the more the number of picture elements of the matrix array 1 are increased, the larger the capacity of the temporary memory B2 required. Further, from the stand point of processing time of the contents or informations, since such above mentioned processing system of the prior art starts the processing after the data of one picture frame is stored in temporary memory B2, the system contains a defect that data processing time becomes long as a natural necessity.